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type ii caller id decoder NW6003 the idt logo is a registered trademark of integrated device technology, inc industrial temperature range july 2002 ? 2002 integrated device technology, inc. dsc-6047/2 fea tures 1200 baud bell 202 and itu-t v.23 frequency shift keying (fsk) demodulation compliant with three specifications: bellcore gr-30-core & sr-tsv-002476 british telecom (bt) sin227 & sin242 cable communication association (cca) tw/p&e/312 bellcore ?cpe alerting signal (cas)? and british telecom ?idle state and loop state tone alert signal? detection ring and line reversal detection high sensitivity with -40 dbv input tone and fsk detection serial data interface to microcontroller 3 v 10% or 5 v 10% operation low power cmos with powerdown mode operating temperature range: -40 c to +85 c packages available: NW6003-xs 24 pin soic (where ?x? is the revision id) figure 1. block diagram oscillator line reverse and ring detector 3 v/5 v detector bias generator interrupt generator guard time dual tone detector fsk demodulator data/timing recovery + - trigin trigrc trigout oscin oscout vref cap pwdn in + in - gs fsken mode dr data dclk cd est st/gt std int description the NW6003 device is a single-chip, 3/5 volt cmos caller id and call waiting detection circuit. it can receive signals following bellcore gr-30-core & sr-tsv-002476, bt sin227 & sin242, and cca tw/ p&e/312 specifications. the NW6003 provides 1200 baud bell 202 and itu-t v.23 fsk demodulation. it allows a microcontroller to extract data from it via a serial interface. in addition, the NW6003 offers idle state and loop state tone alert signal and line reversal detection capability for bt clip, ring burst detection for the cca clip, and ring and cas detection for bellcore cid. the device can be used in feature or cordless phones for bt calling line identity presentation (clip), cca clip and bellcore calling identity delivery (cid) systems. it can also be used in caller id boxes, modem, fax machines, answering machines, database query systems and computer telephony integration (cti) systems. functional block diagram
2 industrial temperature range NW6003 type ii caller id decoder pin informa tion figure 2. pin assignment in+ in- gs vref cap trigin trigrc trigout mode oscin oscout gnd vcc st/gt est std int cd dr da t a dclk fsken pwdn tm 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 1 1 12 name type pin no. description in+ i 1 non-inverting input of the gain adjustable op amp. in- i 2 inverting input of the gain adjustable op amp. gs o 3 gain select output of the gain adjustable op amp. select the op amp gain by adjusting the resistor ratio in the feed-back resistor network. vref o 4 reference voltage. this output is used to bias the input op amp. it is typically vcc/2. cap o 5 capacitor connector. a 0.1 m f decoupling capacitor should be connected between this pin and gnd. trigin i 6 trigger input. this is a schmitt trigger input used for ring detection and line reversal detection. trigrc i/o 7 trigger resistor and capacitor connector. this pin is connected to vcc and gnd through resistor and capacitor. the rc value decides the time delay from trigin going inactive (low) to trigout becoming inactive (high). see fig.6 for reference. trigout o 8 trigger output. this is a schmitt trigger buffer output indicating the detection of line reversal and/or ringing. mode i 9 serial fsk interface mode select. a low level on this pin sets the interface to mode '0', while a high level sets it to mode '1'. oscin i 10 oscillator input. a 3.579545 mhz crystal or ceramic resonator should be connected between this pin and the oscout. it can also be driven by an external clock source. oscout o 11 oscillator output. a 3.579545 mhz crystal or ceramic resonator should be connected between this pin and and oscin. when oscin is driven by an external clock, this pin should be left floating. gnd -- 12 ground. tm i 13 test mode. must be connected to gnd for normal operation.
3 industrial temperature range NW6003 type ii caller id decoder abbreviation index cas ----------------------------------------------------------- cpe alerting signal cds ----------------------------------------------------------- caller display service cid ------------------------------------------------------------ calling identity delivery cidcw ------------------------------------------------------- calling identity delivery on call waiting clip ---------------------------------------------------------- calling line identity presentation cnam -------------------------------------------------------- calling name delivery cnd ---------------------------------------------------------- calling number delivery cnic --------------------------------------------------------- calling number identification circuit co ------------------------------------------------------------- central office cti ----------------------------------------------------------- computer telephony integration te -------------------------------------------------------------- terminal equipment pin informa tion (continued) name type pin no. description pwdn i 14 power down. this is an active high schmitt trigger input. when active, the device enters a minimal power state by disabling all internal functional circuits except trigin, trigrc and trigout . it must be low for normal operation. fsken i 15 fsk enable. when this pin is high, fsk demodulation is enabled. this pin should be set low to disable the fsk demodulator from reacting to extraneous signals such as speech, alert signal etc. dclk i/nc 16 data clock. in mode '0' (mode pin low), this pin is unused. in mode '1' (mode pin high), this pin is an input, data clock is provided by microcontroller. data o 17 data output. in mode '0', data appears on this pin once demodulated. in mode '1', data is shifted out on the rising edge of dclk, which is supplied by microcontroller. dr o/nc 18 data ready output. in mode '0', this pin is unused. in mode '1', this pin indicates to the microcontroller that 8-bit data is ready. microcontroller initializes the dclk signal to read out the data. cd o 19 fsk carrier detect . this is an active low cmos output signal to indicate the presence of in-band fsk signal. int od 20 interrupt. this is an active low open drain output. this pin is used to interrupt the microcontroller when trigout or dr is low, or std is high. it remains low until all three signals become inactive. std o 21 dual tone alert signal delayed steering output. an active high signal to indicate the detection of a "guard time qualified" dual tone alert signal. est o 22 dual tone alert signal early steering output. this pin is an active high output to indicate the detection of dual tone alert signal. st/gt i/o 23 dual tone alert signal steering input/guard time. it's a cmos output and an input of voltage comparator. if the voltage at this pin is greater than voltage threshold (see fig-6), std is asserted high to indicate that a dual tone has been detected. a voltage less than threshold enables the device to accept a new dual tone. external rc are connected to est and vcc pins. vcc -- 24 3/5 v power supply.
4 industrial temperature range NW6003 type ii caller id decoder functional description caller id specs supported the NW6003 is a type ii caller id device with call waiting capability. it supports bellcore, bt and cca specifications. the major differences between above specs are as follows (refer to figure 13, figure 14, figure 15, figure 16 and figure 17): bellcore bellcore gr-30-core and sr-tsv-002476 define the requirement for the signaling services of calling number delivery (cnd), calling name delivery (cnam) and calling identity delivery on call waiting (cidcw). in cnd or cnam service, information of the calling party is embedded in the silent interval between the first and second ringings. the NW6003 can detect the first ringing and then demodulate the incoming bell-202 fsk data. in cidcw service, information about an incoming caller is sent to the subscriber who is engaged in another call. a cpe alerting signal (cas) indicates that a cidcw data is incoming. the NW6003 can detect the alerting signal and demodulate the incoming fsk information which contains cidcw data. the demodulated data is output onto the serial interface. british telecom bt sin227 and sin242 define the signal interface between the central office (co) and the terminal equipment (te) for the caller display service (cds). cds provides clip (calling line identity presentation) that delivers to an idle state (on hook) te the identity of an incoming caller before the first ring. a polarity reversal on the a and b wires (see figure 6) indicates the arrival of a cds call. after that comes an idle state tone a lert s ignal, and then caller id fsk information transmitted in itu-t v.23 format. when the subscriber is engaged in a call, the arrival of information about another incoming call is indicated by a loop state tone alert signal. the NW6003 can detect the line reversal and tone alert signal, it can also demodulate the incoming itu-t v.23 fsk signals. cable communica tion associa tion the cca caller identity specification tw/p&e/312 defines a different cds te interface. in this specificaiton, data is transmitted after a single burst of ringing rather than before the first ringing cycle, as specified in the bt. the idle state tone alert signal is not required in this case. the cca specifies that data can be transmitted in either bell-202 or itu-t v.23 format. the NW6003 can detect the ring burst, and then demodulate either of the fsk format. block description the NW6003 requires a 3.579545 mhz system clock and consists of four major functional blocks: analog input circuit, clip/cid call arrival detection, dual tone alert signal dectection, and fsk demodulation. analog input circuit the input signal is processed by the analog input circuit block, which is comprised of an operational amplifier and a bias source (vref). vref is the output of a low impedance voltage source used to bias the input op amp, and is typically equal to vcc/2. the gain adjustable op amp is also used to select the input gain by connecting a feedback resistor be tween gs and the in- pin. figure 3 shows the necessary connections with the a/b line inputs. in single-ended configuration, the gain adjustable op amp is connected as shown in figure 4. r2 r1 r3 r4 r5 c1 c2 a b NW6003 v ref in+ in- gs differential input amplifier c1=c2 r1=r2 (for unity gain r5=r2) r3=(r4r5)/(r4+r5) voltage gain av = r5/r1 input impedance zin =2 ? r1 2 + (1/ w c)2 figure 3. differential input gain control circuit rin rf c input NW6003 in+ in- gs v ref voltage gain av = rf / rin figure 4. single-ended input gain control circuit
5 industrial temperature range NW6003 type ii caller id decoder clip/cid call arriv al detection figure 6 shows the typical application circuit to detect the clip/cid call arrival signals. the diode bridge works for both single ended and balanced ring signals. r1 and r2 are used to set the maximum loading and must be of some value to achieve balanced loading. the ring signal is attenuated by r1, r3 and r4 resistor devider before being applied to pin trigin. the attenuation value is determined by the detection of minimal ring voltage and maximum noise tolerance between ring/tip and ground. when no signal is applied to telephone line, trigin will be at ground and pin trigout will stay inactive high. if trigin increases from ground to vt+ (schmitt trigger high going threshold voltage), c3 gets discharged, trigrc becomes low and trigout is asserted. the low going trigout can be used to interrupt or wake up the microcontroller. when trigin signal drops below vt- (schmitt trigger low going threshold voltage), c3 will start to charge up through r5c3 time constant. after trigrc pin reaches above the threshhold voltage (vt+), trigout becomes inactive high and it stops to interrupt the microcontroller. to ensure the minimum trigout low interval and to filter the ring signal to get a smooth envelope output, the rc time constant should be greater than the maximum cycle time of the ring signal. ring detection for bellcore: bellcore recommends that the cid fsk data be transmitted between first and second ringings. the circuit in figure 6 will generate a ring envelope signal at pin trigout for the ring voltage of 40 vrms or greater. r5 and c3 are used to filter the ring signal to provide the envelope output. line reversal detection for bt: british telecom uses the line polarity reverse (+15 v to -15v between the two lines slewing in 30 ms) to indicate the arrival of an incoming cds call. when line reverse occurs, trigin increases over vt+ and trigout signal becomes active low. when reversal is over, trigin falls below vt- and trigout returns inactive high. ring burst detection for cca: the cca requires the te to detect a single burst of ringing followed by the fsk data. the ring pulse may varies from 30 to 75 vrms with pulse duration 200 - 450 ms. r1 = 500k r2 = 500k r3 = 200k r4 = 300k r5 = 330k c1= 0.1 m f c2= 0.1 m f n c3 = 0.22 m f tip/a ring/b trig in trigrc trig out NW6003 to microcontroller note: minimal triggerable ring voltage (peak to peak) is: vpp(max ring)= 2(vt+(max)(r1+r3+r4)/r4+0.7) tolerance to noise between tip/ring and vss is: vmax noise= vt+(min)(r1+r3+r4)/r4+0.7 suggested rc component value: 10k w < r5 < 500k w . 47 nf < c3 < 0.68 m f time constant is: t=r5c3in(vcc/(vcc-vt+)) vt+(min) = 0.7 vcc vt+(max) = 0.5 vcc figure 6. clip/cid call arrival detection circuit ring signal trigrc trigout trigin vt+ vt- vt+ figure 5. trigin, trigrc and trigout operation
6 industrial temperature range NW6003 type ii caller id decoder dual tone alert signal detection bt specifies a dual tone alert signal in both idle (on-hook) state and loop (off-hook) state, while bellcore specifies a similar dual tone alert signal called cpe alerting signal (cas) in off-hook state. the low and high tone frequencies of two different systems are as follows: the incoming alert signal goes through anti-alias filter and then is separated into high band and low band by two bandpass filters. the tone detection algorithm examines the filter outputs to validate the arrival of the dual tone alert signal. the est pin becomes active when both tones are detected. the est is only the preliminary indication, it must be qualified by the ?guard time? as required by bellcore and bt (a minimum duration for valid signals). std is the guard time qualified cas/dual tone alert signal detection output, it indicates the correct detection. figure 7 shows the operation of the guard time circuit and figure 8 shows the waveform of the est, st/gt and std pins. the total recognition time is t rec = t dp + t gp , where t dp is the tone present detection time and t gp is the tone present guard time. the total absent time is t abs = t da + t ga , where t da is the tone absent detection time and t ga is the tone absent guard time. the guard time is the rc time constant for the capacitor charge to vcc or discharge to gnd. to get the unequal present and absent guard time, a diode can be connected as shown in figure 9 to provide different rc time constant (varying resistance value) during charging and discharging. figure 9. guard time circuits with unequal present and absent times bt bellcore low tone frequency 2130 hz 1.1% 2130 hz 0.5% high tone frequency 2750 hz 1.1% 2750 hz 0.5% dual tone detected p n + - comparator vcc st/gt e st s td NW6003 figure 7. guard time circuit of dual tone alert signal detection v tgt q1 q2 alerting signal on on on t dp t da t ga t gp v tgt v tgt t rec t abs tip/ ring est st/gt std q1 switch q2 switch figure 8. guard time waveform vcc r1 r2 c NW6003 vcc st/gt est r1 r2 c NW6003 vcc st/gt e st t gp > t ga t gp =r1cin(v cc /(vcc-v tgt )) t ga =r p cin((v cc -vd(r p /r2))/ (v t gt -vd(r p /r2))) r p =r1r2/(r1+r2) vd=diode forward voltage t gp < t ga t gp =r p cin((v cc -vd(r p /r2))/ (v cc -v tgt -vd(r p /r2))) t ga =r1cin(v cc /v tgt ) r p =r1r2/(r1+r2) vd=diode forward voltage
7 industrial temperature range NW6003 type ii caller id decoder fsk demodula tion the key part among the functions offered by NW6003 is fsk demodulation. this function is implemented by several stages: first, the carrier detector provides an indication of the presence of signal at the bandpass filter output; second, the device?s dual mode serial interface allows convenient extraction of the 8-bit data words in the demodulated fsk bit stream. the fsk characteristics are different in bt and bellcore specifications. the bt?s signal frequencies correspond to itu-t v.23; the bellcore frequencies correspond to bell 202. the cca requires that te be able to receive both itu-t v.23 and bell 202 signals. the NW6003 is compatible with both formats. it also meets the signal characteristics by setting the input op amp at unity gain in 5 v operation. the dual tone alert signal, speech and dtmf tones are in the same frequency band as fsk, they will be demodulated and generate false data. to avoid it, fsken pin is used to disable the fsk modulation when fsk signal is not expected. fsk carrier detection the carri er detector provides an indication of the presence of a signal in the fsk frequency band. it detects the presence of a signal of sufficient amplitude at the output of the fsk bandpass filter. if the signal is qualified by a digital algorithm, the cd output becomes low to indicate carrier detection. an 8 ms hysteresis is provided to allow for momentary signal drop out once cd has been activated. and when there is no activity at the fsk bandpass filter output for 8 ms, cd is released. when cd is inactive (high), the raw output of the fsk demodulator is ignored by the fsk data output interface. in mode ?0?, the data pin is forced high. in mode ?1?, the internal shift register is not updated. no dr is generated. if dclk is clocked, data is undefined. serial fsk interf ace the three wire data, dclk and dr form the data interface of the fsk demodulation. the data pin is the serial data pin that outputs data to external devices. the dclk pin is the data clock which is generated by an external device. the dr pin is the data ready signal, also an output from the NW6003 to external devices. this interface provides the mechanism to extract the 8-bit data words in the demodulated fsk bit stream. two modes are selectable via control of the device?s mode pin: mode ?0? (mode pin is low), where data transfer is initiated by the NW6003; mode ?1? (mode pin is high), where the data transfer is initiated by an external microcontroller. mode ?0? in this mode, data transfer is initiated by the NW6003. the device demodulates the incoming fsk signal, and output the data directly to the data pin. figure 24 shows the timing diagram of mode ?0? operation. mode ?1? in this mode, the microcontroller supplies read pulses (dclk) to shift the 8-bit data words out of the NW6003, onto the data pin. the NW6003 asserts dr to denote the word boundary and indicate to the microprocessor that a new word has become available. internal to the device, the demodulated data bits are sampled and stored. after the 8th bit, the word is parallelly loaded into an 8-bit shift register and dr goes low. the contents of shift register are shifted out to data pin on dclk?s rising edge with lsb (least significant bit) out first. if dclk begins while dr is low, dr will return to high upon the first dclk. this feature allows the associated interrupt to be cleared by the first read pulse. otherwise, dr stays low for half a nominal bit time (1/2400 sec) and then returns to high. after the last bit (most signifi cant bit) has been read, additional dclks are ignored. figure 22 shows the timing diagram of mode ?1? operation. itu - t v.23 bell 202 mark freq. (?1?) 1300 hz 1.5% 1200 hz 1% space freq. (?0?) 2100 hz 1.5% 2200 hz 1%
8 industrial temperature range NW6003 type ii caller id decoder other functions power-down mode the device provides the power down feature to reduce the power consumption. by activating the pwdn pin (high), the gain adjustable op amp, oscillator and all other internal circuits besides the ring detection circuit are all disabled. the trigin, trigrc and trigout pins are not affected, the device can still react to call arrival indicator and activate the interrupt to wake up the microcontroller. cr yst al oscilla t or a 3.579545 mhz crystal oscillator or other external clock source is required for NW6003. the crystal can be directly connected between oscin and oscout pins without any external component. if an external clock source is used, oscin pin should be driven by the clock source and oscout pin is left floating or is used to drive other devices. figure 10 shows some applications. NW6003 osc in osc out 3.579545mhz to the next device (b) common crystal connection of several devices sharing one timing source (a) connection of one device with crystal oscillator figure 10. applicaiton of clock driven circuit when the system is first powered up, trigout will be low (c3 at trigrc has no initial charge) and std will be high if pwdn is low (no charge across the capacitor at st/gt pin in figure 7), interrupt signal will be generated. the microcontroller should ignore interrupts from these sources on the initial power up until there is sufficient time to charge the capacitors. also, by asserting pwdn high immediately after system power up, std will become low and no interrupt will be generated. in power-down mode, est and comparator output are forced low, the charging switch will turn on, and the capacitor at st/gt pin will charge up more rapidly. bias vol t age genera t or the bias voltage generator provides a low impedance voltage source equal to vcc/2 on pin vref and is used to bias the op amp. to reduce the noise, a 0.1 m f capacitor should be connected between cap and gnd pins. interrupt the NW6003 provides an open drain interrupt output int to interrupt the microcontroller. either trigout low, std high or dr low will activate the int and it will remain active ?low? until all of these three pins return to an inactive state. the microcontroller should read these pins through input ports to detect the interrupt type ( trigout , std or dr ) and to make the correspondent response. NW6003 osc in osc out NW6003 osc in osc out NW6003 osc in osc out 3.579545mhz
9 industrial temperature range NW6003 type ii caller id decoder applica tion informa tion applica tion circuits figure 11 shows the typical NW6003 application circuit. for 5 v operation, the gain ratio of the op amp is set to unity to optimize the electrical characteristics. as the power supply voltage drops, the threshold of tone and fsk detectors will be lower. to meet the bt and bellcore tone reject level requirements, the gain of the op amp should be adjusted according to the graph in figure 12. it should be noted that the glitch with sufficient amplitude appears on the tip and ring interface will be falsely detected. one way to avoid such false detection is to use the photo-coupler led between the diode bridge and trigin pin. bellcore/bt/cca applica tions the NW6003 supports three specifications: bellcore, bt and cca. figure 13 shows the timing diagram of bellcore on-hook data transmission, and figure 14 shows bellcore off-hook data transmission. the bt operations are shown in figure 15 and figure 16, and the cca operation in figure 17. figure 12. gain ratio as a function of nominal vcc gain ratio nominal vcc(volts) 0.5 0.6 0.7 0.8 0.9 1.0 2 3 4 5 6 7 0.678 gain ratio of op amp = 464k w r1 + r4 figure 11. typical application circuit for vcc = 5v 10%, r1 = r1? = 430 k w , r4 = r4? = 34 k w. for vcc = 3v 10%, r1 = r1? = 620 k w , r4 = r4? = 63 k 4. resistor tolerance 5% and capacitor tolerance 10% unless otherwise specified. crystal frequency 3.579545 mhz with 0.1%tolerance. for bt application, c = 0.1 m f 5%, r2 = r3 = 422k 1%. for bellcore application, c = 0.1 m f 5%, r2 = 266k 1%, r3= 825k 1%. r1 1% r4 1% r1' 1% r4' 1% 464k 1% 60k4 1% 500k 500k 200k 300k 100k 22 nf 5% 22 nf 5% 0.1 m f 5% 0.1 m f 5% 0.22 m f 0.1 m f 0.1 m f c vcc vcc vcc vcc vcc vcc NW6003 tip/a ring/b in+ in- gs vref cap t rigin trigrc trig out mode osc in osc out gnd tm pwdn fsk en dclk data dr cd int std est st/gt vcc 53k6 1% 330k r3 r2 microcontroller
10 industrial temperature range NW6003 type ii caller id decoder ..101010.. data ... ... pwdn fsken cd dr dclk data ch. seizure mark message a b c d e f alerting signal a/b wires trigout 1st ringing 2nd ringing ... ... int note 2 note 5 note 1 note 3 note 2 note 4 figure 13. bellcore on-hook data transmission timing diagram notes: 1) a= 2 sec typ., b= 250 - 500 ms, c= 250 ms, d= 150ms, e depends on data length, max c+d+e = 2.9 - 3.7 sec, f 3 200 ms. 2) in a battery operated cpe, NW6003 may be enabled only after the end of ringing to conserve power. 3) the microcontroller in the cpe powers down the NW6003 after cd goes inactive. 4) the microcontroller times out if cd is not activated on the 2nd ring and puts the device into power-down mode. 5) fsk en may be set always high while the cpe is on-hook. to prevent the fsk demodulator from reacting to other inband signals such as speech, cas or dtmt tones. the designer may choose to set fsken low during the period that fsk signal is not expected.
11 industrial temperature range NW6003 type ii caller id decoder cas mark message cpe off-hook cpe mutes handset and disable keypad cpe unmutes handset and enable keypad a b c d e f g a/b wires pwdn fsken cpe sends ack std ... data cd dr dclk data ... int note 2 note 1 note 3 note 4 note 5 note 6 notes: 1) a= 75 - 85 ms, b= 0 -100 ms, c= 55 - 65 ms, d= 0 - 500 ms, e= 58 - 75ms, f depends on data length, g 50 ms. 2) if ac power is not available, the designer may use the line power when the cpe goes off-hook and use battery power while on-hook. the cpe should also be cid (on-hook) capable . 3) if the end office fails to send the fsk signal, the cpe should disable fsken to unmute the handset and enable the keypad after this interval. 4) when fsk signal is not expected, the fsk en pin should be set low to disable the fsk demodulator. 5) fsk en should be high as soon as the cpe has finished sending the acknowledgement signal ack. 6) fsk en should be low when cd become inactive. figure 14. bellcore off-hook data transmission timing diagram
12 industrial temperature range NW6003 type ii caller id decoder alerting signal ch. seizure mark message ring ..101010.. data ... ... a b c d e f g line reversal a/b wires trigout pwdn std te dc load te ac load fsken cd dr dclk data 15 1 ms 20 5 ms <120 m a 50 - 150 ms < 0.5 ma (optional) current wetting pulse ... ... int zss note 1 note 3 note 4 note 2 notes: 1) a 3 100ms, b=88 - 110 ms, c 3 45 ms (up to 5 sec), d= 80 -262 ms, e= 45 - 75 ms, f 2.5 sec (typ. 500 ms), g 3 200 ms. 2) by choosing t ga =15 ms, t abs will be 15-25 ms (refer to figure 8). current wetting pulse and ac/dc load should be applied right after the std falling edge. 3) ac and dc loads should be removed between 50-150 ms after the end of the fsk signal. the NW6003 may go to power down mode to save power. 4) fsk en should be set low to disable the fsk demodulator, when the fsk signal is not expected. figure 15. bt idle state (on-hook) data transmission timing diagram
13 industrial temperature range NW6003 type ii caller id decoder alert signal mark message te in loop state (off-hook) speech path disabled speech path restored a b c d e f g a/b wires pwdn fsken ack std ... data cd dr dclk data ... int start point h note 1 note 2 note 3 note 4 note 5 note 6 notes: 1) a= 40 - 50 ms, b= 80 - 85 ms, c 100 ms, d= 65 - 75 ms, e= 5- 100ms, f = 45 - 75 ms, g depends on data length, h 100 ms. 2) if ac power is not available, the designer may use the line power when the te goes into loop state (off-hook) and use battery power while on-hook. 3) if the end office fails to send the fsk signal, the te should disable fsken to unmute the handset and enable the keypad after this interval. 4) when fsk signal is not expected, the fsk en pin should be set low to disable the fsk demodulator. 5) fsk en should be high as soon as the te has finished sending the acknowledgement signal ack. 6) fsk en should be low when cd become inactive. figure 16. bt loop state (off-hook) data transmission timing diagram
14 industrial temperature range NW6003 type ii caller id decoder ch. seizure mark data packet a b c d e f alerting signal a/b wires trigout ring burst ..100110.. data ... ... pwdn te dc load te ac load fsken cd dr dclk data 25 ms 3 8 ms 50 - 150 ms 250 - 400 ms int 1st ring note 2 note 1 note 2 note 3 note 4 figure 17. cca caller display service timing diagram notes: 1) a = 200 - 450 ms, b 3 500 ms, c= 80 - 262 ms, d= 45 -262 ms, e 2.5 s (typ. 500 ms), f 3 200 ms. 2) trigout indicates the ring envelope. 3) ac and dc loads should be applied between 250 - 400 ms after the ring burst and should be removed between 50 to 150 ms after the end of fsk signal. 4) fsk en should be set low when fsk signal is not expected.
15 industrial temperature range NW6003 type ii caller id decoder maximum ra ting - exceeding the following listed values may cause permament damage. power supply voltage: -0.3 v to 7 v voltage on any pin other than supplies: gnd - 0.3 v to vcc + 1 v current at any pin other than supplies: 20 ma storage temperature: -65 c to +150 c recommended opera ting conditions operating temperature: -40 c to +85 c power supply voltage: 3 v 10% or 5 v 10% clock frequency: 3.579545 mhz 0.1% input voltage: 0 v to vcc cr y st al s pecifica tions frequency: 3.579545 mhz resonancy tolerance: 0.1%( -40 c to +85 c) resonance mode: parallel load capacitance: 18 pf maximum series resistance: 150 w maximum drive level(mw): 2 mw dc electrical characteristics test 1: all inputs are vcc/gnd except for oscillator pins. no analog input. output unloaded. pwdn = vcc. test 2: all inputs are vcc/gnd except for oscillator pins. no analog input. ouput unloaded. pwdn = gnd, feken = vcc. parameter pin description min typ max units test conditions i ccs power supply standby current 0.5 10 m a test 1 i cc vcc operating supply current vcc = 5 v 10% vcc = 3 v 10% 2.5 1.8 3.8 2.7 ma ma test 2 v t+ trig in schmitt trigger input high threshold 0.5vcc 0.7vcc v v t - trigrc pwdn schmitt trigger input low threshold 0.3vcc 0.5vcc v v hys schmitt hysteresis 0.2 v v ih dclk mode cmos input high voltage 0.7vcc vcc v v il fsk en cmos input low voltage gnd 0.3vcc v i oh trig out , dclk , data, dr , cd , std, est, st/gt output high sourcing current - 0.8 ma v oh =0.9vcc
16 industrial temperature range NW6003 type ii caller id decoder parameter pin description min typ max units test conditions i ol trigout , dclk, data, dr , cd , std, est, st/gt, trigrc , int output low sinking current 2 ma v ol = 0.1vcc iin1 in+, in - , trigin input current 1 m a iin2 pwdn, dclk mode, fsken input curren t 10 m a v in = vcc to gnd i oz 1 trigrc output high impedance 1 m a i oz 2 st/gt current 5 m a v out = vcc to gnd i oz 3 int 10 m a vref vref output voltage 0.5vcc - 0.05 0.5vcc+ 0.05 v no load rref output resistance 2 k w v tgt st/gt comparator thr eshold voltage 0.5vcc - 0.05 0.5vcc+ 0.05 v dc electrical characteristics (continued) parameter description min typ max units notes f l low tone frequency 2130 hz nominal frequency f h high tone frequency 2750 hz nominal frequency fda frequency deviation accept 1.1% within this range, tones are accepted. fdr frequency deviation rej ect 3.5% outside this range, tones are rejected. sigac accept signal level per tone - 40 - 37.78 - 2 0.22 dbv dbm sigrj reject signal level per tone - 46 - 43.78 dbv dbm the gain setting as in figure 3. production tested at 3 v 10%, or 5 v 10%. ta positive and negative twist accept # 7 db snr signal to noise ratio 20 db both tones have the same amplitude and at nominal frequencies. band limited random noise 300 - 3400 hz. measurement valid only when tone is present. ac electrical characteristics dual tone alert signal detection # twist = 20 log ( f h amplitude / f l amplitude ).
17 industrial temperature range NW6003 type ii caller id decoder ac electrical characteristics (continued) gain adjust able op amp parameter description min typ max units test conditions i in input leakage current 0.8 m a gnd v in vcc r in input resistance 15 m w v os input offset voltage 25 mv psrr power supply rejection ratio 45 db 1khz ripple on vcc cmrr common mode re jection 40 db v cmmin v in v cmmax a vol dc open loop voltage gain 40 db f c unity gain bandwidth 0.3 mhz v o output voltage swing 0.4 vcc - 0.4 v load 3 50 k w c l maximum capacitive load (gs) 100 pf r l maximum resistive load (gs) 50 k w v cm common mode range voltage 1.0 vcc - 1.0 fsk detection parameter description min typ max units notes id input detection level - 40 - 37.78 10.0 - 8 - 5.78 398.1 dbv dbm mvrms production tested at vcc =3v 10%, or 5v 10%. both mark and space have the same amplitude. tr transmission rate 1188 1200 1212 baud fm ark input frequency detection bell 202 ?1? (mark) 1188 1200 1212 hz fspace input frequency detection bell 202 ?0? (space) 2178 2200 2222 hz fmark input frequency detection itu - t v.23 ?1? (mark) 1280.5 1300 1319.5 hz fspace input frequency detection i tu - t v.23 0 (space) 2068.5 2100 2131.5 hz ta positive and negative twist accept * - 10 10 db snr signal to noise ratio 20 db both mark and space have the same amplitude and at nominal frequencies. band limited random noise: 200 - 3400 hz. present only when fsk signal is present. # * twist = 20 log ( f h amplitude / f l amplitude ). # bt band is 200-3400 hz, while bellcore band is 0-4 khz. notes: dbv = decibels above or below a reference voltage of 1 vrms. dbm = decibels above or below a reference power of 1 mw into 600 ohms, 0 dbm = 0.7746 vrms.
18 industrial temperature range NW6003 type ii caller id decoder ac timing characteristics power up/down and fsk detection parameter description min typ max units test conditions t1 power up time 50 ms t2 power down time 1 ms t3 input fsk to cd low delay 25 ms t4 input fsk to cd high delay 8 ms t5 hysteresis 8 ms dual tone alert signal parameter description min typ max units test conditions t6 alert signal present detect time 0.5 10 ms t7 alert signal absent detect time 0.1 8 ms pwdn oscout t1 t2 figure 18. power up/down timing figure 19. fsk detection time tip/ring cd fsk signal t3 t4 tip/ring est alert signal t6 t7 figure 20. dual tone alert signal detection time
19 industrial temperature range NW6003 type ii caller id decoder parameter description min typ max units test conditions t11 dclk cycle time 1 m s t12 dclk high time 0.3 m s t13 dclk low time 0.3 m s t14 dclk rise time 20 ns t15 dclk fall time 20 ns t16 dclk low setup to dr 500 ns t17 dclk low hold time after dr 500 ns ac timing characteristics (continued) serial interf ace (mode ?1?) dclk t13 t14 t12 t15 t11 figure 21. dclk timing in mode ?1? b7 b0 b1 b2 b3 b4 b5 b6 b7 b6 b7 b0 b1 stop start stop b0 nth byte (n-1)th byte nth byte (n+1)th byte t16 t17 internal demodulated bit stream dr dclk data note 1 note 2 start b2 b3 b4 b5 b6 b7 figure 22. serial data interface timing in mode ?1? notes: 1. dclk clears dr . 2. dr not cleared by dclk, low for a maximum time of 1/2 bit width.
20 industrial temperature range NW6003 type ii caller id decoder b7 1 0 b0 b1 b2 b3 b4 b5 b6 b7 1 0 b0 b1 b2 b3 b4 b5 b6 b7 1 0 b0 b1 b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b7 tip/ring data stop stop stop stop start start start start start start t21 nth byte (n+1)th byte nth byte (n+1)th byte figure 24. serial data interface timing in mode ?0? parameter description min typ max units test conditions d r data rate 1188 1200 1212 baud 1 t21 input fsk to data delay 1 5 ms t22 data rise time 200 ns 2 t23 data fall time 200 ns 2 serial interf ace (mode ?0?) test conditions: 1. fsk input data at 1200 12 buad. 2. load of 50 pf. data t23 t22 figure 23. data output timing in mode ?0?
21 corporate headquarters for sales: for tech support: 2975 stender way 800-345-7015 or 408-727-6116 408-330-1552 santa clara, ca 95054 fax: 408-492-8674 email: telecomhelp@idt.com www.idt.com figure 25. NW6003-xs 24 pin soic package diagram phy sical dimensions in millimeters notes: 1) all dimensions in inches 2) form radius min. .010 but not to exceed .030 3) lead tip coplanarityafter form to be within .004 4) ref. jedec ms-13 0.298 0.003 0.406 0.010 0.018 typ. typ. 0.101 0.003 0.604 0.005 0.008 0.003 0.015 45 deg 5 deg typ. 0.016 min. 0.050 max.

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